This invention relates to a majority circuit to suitably be used for a coding system, a neuro chip, a logic circuit or a fault tolerant system and, more particularly, it relates to a majority circuit comprising CMOS inverters.
A majority logic is a basic logic typically required for the coding technology and also in an artificial neural network. It is a logic adapted to output "1" when the number of inputs of "1s" is greater than that of inputs of "0s" and output "0" when the opposite is true, provided that it receives a binary value of "1" or "0" as input at a time. It may be so arranged with a majority circuit that "1" corresponds to logical "true" and "0" corresponds to logical "false" or "1" corresponds to V.sub.DD (supply voltage) [V] and "0" corresponds to 0 (ground voltage) [V].
Conventional majority circuits comprising a digital circuit are formed typically by combining a plurality of exclusive ORs (not shown). However, since it is difficult to realize a multi-input gate in a digital circuit, a multi-input majority circuit is inevitably be a multi-stage circuit that is accompanied by the problem of an increased number of stages and delay.
A majority circuit using a CMOS inverter as shown in FIG. 4 has been proposed as means for solving this problem (Charng Long Lee et al. "A novel design of binary majority gate and its application to median filtering" 1990 IEEE International Symposium on Circuits and Systems, 570-3, vol. 1, 4, xxxix+3289 1990, pp. 570-573).
This circuit comprises a voltage divider (initial stage) and an output buffer (final stage). A plurality of (N in FIG. 4) CMOS inverters, each comprising a PMOS transistor 21 and an nMOS transistor 22 is connected in series between the supply voltage V.sub.dd and the ground. Their gates 23, 24 are connected with each other to form an input terminal. And the outputs of the CMOS inverters are connected with each other to produce the node M. The node M is connected to the input 29 of an output CMOS inverter 28 also comprising a PMOS transistor 25 and an nMOS transistor 26. Thus, the result of the majority decision is produced from the output (V.sub.out) 30 of the output CMOS inverter 28.
With the circuit illustrated having inputs (x.sub.1, x.sub.2, . . . , x.sub.N) as shown in FIG. 4, a potential obtained by a division of the voltage using the ratio of the ON-state resistance of the nMOS transistors of the CMOS inverters receiving "1s" at the respective inputs and the ON-state resistance of the pMOS transistors of the CMOS inverters receiving "0s" at the respective inputs appears at the node M.
If the ON-state resistance of each pMOS transistor and that of each nMOS transistors are equal to each other, the potential of the node M is supposed to fall by V.sub.dd /n when an input "1" is added. However, in reality, there exists a "zone" where the potential of the node M "varies remarkably" due to the non-linear characteristic of the pMOS transistor and the nMOS transistor.
Meanwhile, the inversion threshold value V.sub.th of the output CMOS inverter 28 is so selected as to be between the potential when the number of inputs of "1s" is "greater by one" than that of inputs of "0s" (where the potential of the node M is expressed by V.sub.M1) and the potential when the number of inputs of "1s" is "smaller by one" than that of inputs of "0s" (where the potential of the node M is expressed by V.sub.M2). Then, for the majority circuit to operate properly, the requirement (1) of V.sub.M1 &lt;V.sub.th &lt;V.sub.M2 and the requirement (2) that the zone where the potential of the node M "varies remarkably" is found between V.sub.M1 an V.sub.M2 should be met.
The characteristic properties of the nMOS transistors and those of the pMOS transistors of the initial stage for dividing the voltage should be adjusted to meet the requirement (1), whereas the MOS transistors of the initial stage for dividing the voltage and those of the final stage have to be adjusted in a coordinated manner to meet the requirement (2). However, since the characteristics of MOS transistors vary from circuit to circuit as a function of the manufacturing conditions and other factors, it is practically impossible to control them in the design stage. Therefore, the CMOS majority circuit is accompanied by a problem that the arithmetic processing operation cannot satisfy the required level of precision when the number of inputs is increased to consequently reduce the safety margin of operation.
As pointed out above, a majority logic is a basic logic typically required for the coding technology and also in an artificial neural circuit. A majority logic circuit can be formed by combining a plurality of exclusive OR elements and utilizing the technique of digital circuit as described above in terms of conventional technology or by using a plurality of CMOS inverters connected in parallel and an output buffer as described above as a recent development.
However, a majority logic circuit formed by using exclusive OR elements is accompanied by the difficulty with which a multi-input gate is realized that by turn gives rise to the problem of an increased number of stages and delay. On the other hand, a majority circuit formed by combining CMOS inverters is accompanied by an increased number of inputs that reduces the safety margin of operation and the difficulty of controlling the characteristics of the nMOS transistors and the pMOS transistors of the CMOS inverters that vary remarkably to degrade accuracy.
In view of the above circumstances of the prior art, it is therefore the object of the present invention to provide a majority circuit comprising CMOS inverter circuits that include analog circuits and are adapted to automatically adjust the variances in the MOS characteristics that inevitably arise in the manufacturing process. Such a majority circuit can have a large fan in that operates at high speed and is highly integrated in a small area. A majority circuit according to the invention can suitably be used for a communication LSI, a neuro chip or a fault tolerant system.